Advanced Out-of-Order RISC-V Processor

- Designed a pipelined processor in SystemVerilog for the RISC-V ISA using P6 style renaming, an N-way superscalar design, early tag broadcast, early branch resolution, and GShare branch prediction.

- Also incorporated instruction prefetching, non-blocking instruction and data caches (N-way set-associative and banked, respectively), a victim cache, and a load-store queue with forwarding.

- Achieved a clock frequency of 93.75MHz and an average CPI of 1.7 on a suite of programs including Alexnet, sorting algorithms, and geometric functions.

Roll Over Beethoven: A Cloth Piano

- A foldable, portable piano/keyboard. It comprises the core instrument with cloth keys (on foldable card paper for the prototype), a graphics display (for feedback and tutorials), and a sustain pedal.

- Wrote drivers for the sensors and display + synthesized different timbres + created a tutorial in C.

- Code.

Formal Verification of FtTokenCMP

- Formally verified FtTokenCMP, a fault-tolerant, token-based cache coherence protocol using Murphi.

- Code.

Course Autograder for FPGA design verification, EECS 270

- Co-developed testing frameworks in Verilog, set up Docker environment, and wrote testbenches to verify student designs.

- Deployed on autograder.io.

FPGA Design Projects

- Designed a four function calculator, traffic lights controller and carry lookahead adder.

- Deployed and verified on Altera DE2-115 boards.

Robotic Planning and Controls Projects

- iLQR implementation in Pytorch for the inverted double-pendulum on a cart.

- MPC and MPPI for linearizing cartpole and robot arm dynamics.

- Dynamics from state measurements, with Gaussian processes.

Misc Class Projects in C/C++

- RISC-V assembler, simulator, linker

- Pipeline and cache simulators in C

- Tarjan's pairing heap

- SQL-like relational database

- Among Us simulator with optimal TSP

- Seam-carving for image resizing

- Piazza posts classifier

- Plants vs Zombies simulator

- Euchre simulator